In the first CAN FD Plug-Fest, Bosch, Peak and Vector proofed the interoperability of their CAN FD implementations. The FPGAs implementing the CAN FD data link layer as submitted for international standardization were tested using different network topologies and transmission speeds. All nodes used a 40-MHz clock frequency, an arbitration bit-rate of 500 kbit/s sampled at 80%, and a data-phase bit-rate of 4 Mbit/s sampled at 60%. The tests were performed with different busloads up to 100%. The three nodes communicated in bus-line (9 m) and passive star topologies (2 x 3 m and 1 x 6 m). The passive star was terminated with 60 Ohm at the center point. The next CAN FD plug-fest will take place in September. Parties interested in participation may contact the CAN in Automation (CiA) office. CiA plans a permanent CAN FD test environment for interoperability tests.
The CiA working group specifying CAN FD device and system design recommendations proposes a ration of 1:8 for arbitration/data-phase speed. In addition, the group will recommend bit-timings for different topologies as well as configuration registers for the CAN FD protocol controllers. CAN FD implementations should be clocked by 80, 40, or 20 MHz in order to minimize timing problems.